1. Field of the Invention
The present invention relates generally to the field of sense amplifiers which are used to sense differential voltages and amplify them to full swing, thus identifying the data value contained in the selected memory cell. This application claims the benefit of priority of U.S. Provisional Patent Application No. 61/350,862 filed Jun. 2, 2010 which is incorporated herein by reference in its entirety.
2. Prior Art
Embedded memories are a vital building block in integrated circuits. Static Random Access Memory (SRAM) arrays are a preferred method of implementing embedded memories owing to higher speed, robust design, and ease of integration. In a modern system-on-a-chip (SOC), SRAM arrays may occupy more than half of the die area and are very important in terms of area, yield, reliability and power consumption. As such, there is great motivation to improve the performance of SRAM arrays.
Referring to
FIG. 1, the architecture of an SRAM array is broadly described. In an SRAM array a plurality of memory cells are connected to a plurality of bit lines. In
FIG. 1 the array shown has N rows and M columns, and therefore N×M memory cells. Each memory cell is connected to one of a plurality of word lines (WL), which are arranged in a direction perpendicular to the bit lines. Only one word line is active at a time. A row decoder takes in address information and decodes this in order to activate a single row by enabling that rows wordline signal. Similarly the column decoder takes in address information and activates the necessary columns. The number of columns activated depends on the size of the word in the context of the system. For example, the system may have a 32 bit word, and in that case 32 columns would be activated as a time. Sense amplifiers are used during a read operation to take the differential signals on the bit lines and output full swing data which represents the value of the data stored in the selected SRAM cell. Each column may comprise a sense amplifier, or column multiplexors can be used to multiplexing the bit lines in the columns into a single set of sense amplifiers, thereby reducing the required number of sense amplifiers. The column decoder also sends information to the write circuitry, which is used to write data into a selected SRAM cells during a write operation.
Referring to
FIG. 2, the architecture of a single column is described in more detail. A column may comprise precharge circuitry, a plurality of SRAM cells, a plurality of word lines (WL), differential bit lines (BL and BLB), a column multiplexor and a sense amplifier. The circuitry for the write operation is neglected, as it does not relate to the invention. When the SRAM array is not active (i.e. no read or write operation) the precharge circuitry is enabled, thus keeping the voltages on the bitline high. When a read operation is taking place the precharge circuitry is disabled and a single wordline signal is enabled. When the wordline signal is enabled, a single SRAM cell is able to affect the voltage on the bit lines. The circuitry of the most common SRAM cell, the 6T cell, is illustrated in
FIG. 2. An SRAM cell comprises a latch where one side stores a high logical value, and the other side stores a low logical value. When the access transistors of the SRAM cell are enabled by the wordline signal (WL) the SRAM cell affects the bit lines by discharging one of the bit lines, BL or BLB, depending on which side of the latch stores the low logical value. An SRAM cell is designed to be as small as possible in order that the largest number of memory cells, and therefore information, can be contained in a given area. As the SRAM cell is small, its transistors are intrinsically weak. The bit lines must span the entire height of the column and are connected to each SRAM cell in the column. As such the bit lines have a high intrinsic parasitic capacitive load. The result of the weak SRAM cell and the large capacitance of the bit lines is that is takes a long time for the SRAM cell to fully discharge. Moreover, once discharged the bit line must be re-charged by the pre-charge circuitry, which results in a non-trivial power dissipation. The purpose of the sense amplifier is to detect a small differential signal on the bit lines and amplify it in order to identify the data value stored in the selected SRAM cell.
Referring to
FIG. 3(a), the schematic of a voltage mode sense amplifier is shown, and
FIG. 3(b) shows waveforms which illustrate its operation. The read operation begins with the wordline signal WL being enabled. This results in a differential voltage being generated on the bit lines. The sense amplifier is enabled via the control signal SA. In this sense amplifier the bit lines are connected to the gates of two NMOS transistors, MN3 and MN4 and as such the voltages on the bit lines BL and BLB control the effective resistance of these NMOS transistors. Before the sense amplifier is enabled the control signal SA is low, and therefore the latch comprising MN1, MN2, MP1, and MP2 is equalized by way of transistor MP3. This means that the voltages on nodes OUT and OUTB are the same and are in this case are assumed to be equal to VDD. When the sense amplifier is enabled the equalization transistor MP3 is disabled and a path to ground is activated by way of transistor NMOS MN5. However the impedance of the path from node OUT to VSS will be different than the path from node OUTB to VSS, based on the voltages BLB and BL. Referring to
FIG. 3(b), in this case the voltage on bitline BLB is slightly lower than the voltage on bitline BL, and as such the resistance from OUT to VSS will be higher than the resistance from OUTB to VSS. This means that node OUTB will begin discharging faster than node OUT, and due to the regenerative action of the latch this difference will be amplified to full swing, with the voltage on node OUT resolving to VDD and the voltage on node OUTB resolving to VSS.
Referring to
FIG. 4(a), the schematic of a current mode sense amplifier is shown, and
FIG. 4(b) shows waveforms which illustrate its operation. The read operation begins with the wordline signal WL being enabled. This results in a differential voltage being generated on the bit lines. The sense amplifier is enabled via the control signal SA. In this sense amplifier the bit lines are connected to the drains of two PMOS transistors. MP4 and MP5. The sources of transistors MP4 and MP5 are in turn connected to nodes OUT and OUTB. Before the sense amplifier is enabled the control signal SA is low, and therefore the latch comprising MN1, MN2, MP1, and MP2 has no path to VSS. Before the sense amplifier is enabled transistors MP4 and MP5 couple the voltage on the bitlines BL and BLB into the nodes OUT and OUTB. When the sense amplifier is enabled a path to ground is activated by way of NMOS transistor MN5. When the sense amplifier is enabled the transistors MP4 and MP5 are disabled, decoupling the internal nodes of the sense amplifier OUT and OUTB from the bitlines BL and BLB. While the bitlines are decoupled from the internal nodes of the sense amplifier the last voltage on the bitlines before the sense amplifier is enabled becomes the initial condition for the latch, and should define the way in which the sense amplifier will resolve. Referring to
FIG. 4(b), in this case the voltage on bitline BLB is slightly lower than the voltage on bitline BL, and as such when the sense amplifier is enabled the voltage on node OUT is slightly higher than the voltage on node OUTB. Due to the regenerative action of the latch this difference will be amplified to full swing, with the voltage on node OUT resolving to VDD and the voltage on node OUTB resolving to VSS.
Referring to
FIG. 5(a), the schematic of a conventional sense amplifier is shown, and
FIG. 5 (b) shows waveforms which illustrate its operation. The read operation begins with the wordline signal WL being enabled. This results in a differential voltage being generated on the bit lines. The sense amplifier is enabled via the control signal SA. In this sense amplifier the bit lines are coupled to the sense amplifier through the sources of two PMOS transistors, MP1 and MP2. The drains of the transistors MP1 and MP2 are in turn connected to nodes OUT and OUTB. Before the sense amplifier is enabled the control signal SA is low, and therefore the latch comprising the set of transistors MN1, MN2, MP1, and MP2 is equalized by way of transistors MP3 and MP4. This means that at the instant the sense amplifier is enabled the voltages on nodes OUT and OUTB are the same and are in this case are assumed to be equal to the supply voltage VDD. When the sense amplifier is enabled the equalization transistor MP3 is disabled and a path to ground is activated by way of NMOS transistor MN5. Once the path to ground is activated the latch comprising the set of transistors MN1, MN2, MP1, and MP2 begins to resolve. Ideally the resolution of the sense amplifier will be determined by the differential bitline voltage, however for this sense amplifier the bitlines are coupled through transistors MP1 and MP2, which are disabled due to the voltage at their gates being initially set to the high level VDD. The voltage OUT and OUTB will begin to discharge and will eventually reduce to a level low-enough that the transistors MP1 and MP2 are turned on, and this allows the differential bitline voltages to have an effect on the resolution of the latch. However, until this happens the resolution of the latch will be determined by any transistor mismatch between transistors MN1 and MN2. In modern technologies mismatch can be very large, and as such this sense amplifier suffers from poor yield.
CMOS technologies continue to scale to smaller geometries. This allows for greater performance and density, however it brings with it an increase in the variability of the process. In earlier generations of CMOS processes variability was primarily systematic, however as feature sizes scale below 100 nm, random variability has become increasingly problematic. Systematic variability causes circuits to vary from die to die or wafer to wafer, while random variability can cause variations in the properties of even transistors which are adjacent to one another. Sense amplifiers are affected by process variability, and the most significant effect is the creation of a voltage offset. A voltage offset in a sense amplifier means that the circuit is inclined to resolve in a particular direction. This can often result in an incorrect decision. For example, if a sense amplifier has an offset voltage of 50 mV and the differential voltage on the bit lines is only 40 mV, the decision the sense amplifier makes is due the its offset voltage, not due to the differential voltage on the bit lines. The differential voltage on the bit lines must be larger than the offset voltage of the sense amplifier in order for the sense amplifier to correctly resolve.
The effect of variability is related to yield, performance and power. All circuits which comprise an embedded memory are negatively affected by variability. For example, variability will result in SRAM bit cells which are weaker, and in turn can generate less differential voltage on the bit lines. As previously described variability can affect a sense amplifier by creating offset voltages which make it more inclined to make incorrect decisions. If an SRAM array cannot correctly identify the information contained in the SRAM cell then it is not able to function as an embedded memory, and as such this reduces the yield of the SoC. In order to combat the effects of variability the length of time the word line is activated can be increased. This will allow more time for the SRAM cell to generate a differential voltage on the bit lines and thus the input voltage to the sense amplifier will be larger. However, this has a negative impact on the timing performance of the embedded memory, and as such on the timing performance of the SOC. Moreover, for those SRAM cells which function correctly the longer wordline signal will result in increased power dissipation. In order to combat the effects of variability the transistor sizes can also be increased, however this leads to a less are efficient design, which increases cost and is highly undesirable.
Referring to
FIG. 6(a), the schematic of a conventional sense amplifier is shown, and
FIG. 6(b) shows waveforms which illustrate its operation. The read operation begins with the wordline signal WL being enabled. This results in a differential voltage being generated on the bit lines. The sense amplifier is enabled via the control signal SA. In this sense amplifier the bit lines are coupled to the sense amplifier through the sources of two PMOS transistors, MP1 and MP2. The drains of the transistors MP1 and MP2 are in turn connected to nodes OUT and OUTB. Before the sense amplifier is enabled the control signal SA is low, and therefore the latch comprising the set of transistors MN1, MN2, MP1, and MP2 is equalized by way of transistor MN3. This means that at the instant the sense amplifier is enabled the voltages on nodes OUT and OUTB are the same. When the sense amplifier is enabled the equalization transistor MN3 is disabled. The latch comprising MN1, MN2, MP1, and MP2 is gated by transistors MP3 and MP4, which means that while MP3 and MP4 are disabled the latch cannot resolve, but rather stays in a metastable state. Once the control signal SA is set to enable the latch comprising the set of transistors MN1, MN2, MP1, and MP2 begins to resolve. Ideally the resolution of the sense amplifier will be determined by the differential bitline voltage.
Referring to
FIG. 10(a), the schematic of a conventional sense amplifier is shown. The sense amplifier in FIG. 10(a) is similar to the sense amplifier in FIG. 6(a), however the inputs are into the drains of NMOS transistors rather than PMOS transistors, and the gating transistors are also NMOS, rather than PMOS transistors.
Referring to
FIG. 10(b) shows waveforms which illustrate the operation of the sense amplifier in FIG. 10(a).